Can panel-level fan-out packaging (FOPLP) solve the CoWoS production shortage? Analyzing the area benefits and warpage challenges of square substrates.

Driven by the explosive growth in demand for generative AI and high-bandwidth computing, TSMC's CoWoS (Chip-on-Wafer-on-Substrate) capacity has become a key strategic resource that global tech giants are vying for. In order to break through the capacity ceiling of 300 mm wafer-level advanced packaging, the semiconductor and display supply chains are turning their attention to "Fan-Out Panel-Level Packaging (FOPLP)," attempting to alleviate the supply and demand imbalance of high-end chip packaging by leveraging the area advantage of large-size square substrates.

Let's get straight to the core question:While FOPLP cannot directly replace the top-tier CoWoS capacity in the short term, it can generate a powerful "dimension reduction and diversion" effect on the advanced packaging landscape. The reason is that flagship AI chips (such as NVIDIA Blackwell or AMD Instinct series) require up to 8 or more high bandwidth memory (HBM) chips, which rely on micron and sub-micron level (0.4 µm to 0.8 µm linewidth and spacing) silicon interposers for ultra-high density interconnection. This is a physical step that FOPLP, which uses organic polymers as dielectric layers and generally has linewidth and spacing of 2 µm to 5 µm, cannot completely cross.

However, FOPLP brings disruptive cost and area advantages. Through large-size square substrates of 510 mm × 515 mm or even 600 mm × 600 mm, not only is the single-batch processing area increased by 3.7 to 5.1 times, but the edge geometry utilization rate of the substrate also leaps from 85% in traditional circular wafers to over 95%. This article will take you through a comprehensive breakdown of the engineering challenges and real-world applications behind this semiconductor shape revolution, covering aspects such as geometry utilization, material thermal expansion coefficient (CTE) mismatch, warpage mechanics, and die shift.

The root cause of CoWoS's tight production capacity: physical bottlenecks in wafer-level packaging and silicon interposers.

To understand why FOPLP is so popular in the industry, we must first understand the structural characteristics and capacity bottlenecks of CoWoS.

Mainstream CoWoS (especially CoWoS-S used in flagship AI chips) adopts a "2.5D heterogeneous integration" architecture. Its structure can be broken down into three layers: the top layer is the computing logic die (SoC / GPU / ASIC) and multiple high-bandwidth memory (HBM); the middle layer is a whole piece of "silicon interposer" made of pure silicon; and the bottom layer is a traditional organic flip-chip ball gate array (FCBGA) substrate.

The core task of the silicon interposer is to establish thousands of ultra-high bandwidth, ultra-low latency parallel data channels between the logic chip and the HBM through micron-level metal lines and through-silicon vias (TSVs). To achieve sub-micron level linewidth and spacing (L/S up to 0.4 µm / 0.4 µm), the silicon interposer must be manufactured in a 12-inch (300 mm) wafer foundry using advanced semiconductor stepper, chemical mechanical polishing (CMP), and deep reactive ion etching (DRIE) equipment.

This extremely precise structure brings about stringent production capacity bottlenecks:

• Reticle Limit and splicing challengesThe single exposure field of a standard semiconductor stepper is typically about 26 mm × 33 mm (approximately 858 mm²). Next-generation AI modules often require an interposer layer 2.5 to 3.3 times the mask area (over 2,000 to 3,000 mm²), which must be achieved through multiple precise mask stitching techniques. This significantly increases the operating time of the exposure machine and limits production speed.
• Large-size wafer cutting lossOn a circular silicon wafer with a diameter of 300 mm (approximately 70,686 mm²), after deducting the edge exclusion zone and geometric cutting waste, only a dozen or so huge interposers with an area of over 50 mm × 50 mm can be cut. Even the smallest localized particle defects in the wafer result in a significant loss in yield.
• Equipment capital expenditure and capacity expansion cycleSilicon interposer manufacturing occupies valuable 12-inch wafer fab cleanrooms and high-end process equipment, resulting in a production expansion cycle of 12 to 18 months or more, making it impossible to keep up with the explosive chip demand for AI servers in a short period of time.

To further clarify the complete evolution of semiconductor packaging from traditional leadframes and wire bonding to 2.5D/3D heterogeneous integration, please refer to the information on this website.Advancements in packaging technologyAnalysis of the technological evolution.

What is Panel-Level Fan-Out Package (FOPLP)? A Size Revolution for Square Carrier Boards

The basic concept of fan-out packaging is to bypass the costly IC substrate. The diced die is attached face down to a temporary substrate, and then molded using epoxy molding compound (EMC) to form a reconstituted substrate. Subsequently, multiple thin-film redistribution layers (RDLs) are fabricated on the die surface and the molded area, allowing metal signal contacts to extend (fan-out) beyond the chip body. Micro-solder balls are then added to complete the external interconnects.

When the reconstructed substrate is a 300 mm circular wafer, it is called "Wafer-level Fan-Out Package (FOWLP)," and TSMC's well-known InFO (Integrated Fan-Out) belongs to this category.

"Fan-out Panel Package (FOPLP)" directly replaces the carrier from a 300 mm diameter circular wafer to one with a side length of 500 mm to 700 mm or more.Large rectangular glass, metal, or organic panels.

The table above clearly shows the leap in geometric scale: a 510 mm × 515 mm panel is equivalent to 3.7 12-inch wafers; while a 600 mm × 600 mm panel is 5.1 times the size of a 12-inch wafer. This means that in single process steps such as coating, exposure, electroplating, and molding, the number of wafers processed in a single machine operation is increased several times.

Circle vs. Square: A Geometric Problem of Area Utilization and Edge Loss

Besides the dramatic increase in total area, FOPLP's most compelling original value lies in the fundamental improvement of "Geometric Area Utilization Rate".

In wafer fabrication and wafer-level packaging, semiconductor components are all square or rectangular, but the carrier is a circular silicon wafer. There is an unavoidable "chord loss" between the circular geometric edges and the rectangular die.

In addition, to avoid chemical residues, edge scratches, and uneven adhesive thickness, a 3 mm to 5 mm "edge exclusion zone" must be maintained around the outer edge of the wafer. When the package area is small (e.g., a 5 mm × 5 mm mobile phone RF chip), the wafer utilization rate is approximately between 82% and 85%; however, as the package moves towards larger chip modules (e.g., 40 mm × 40 mm or larger), the number of areas where the arc perimeter cannot form a complete rectangle increases significantly, and the actual effective area utilization rate often falls below 75%.

In contrast, square panels and rectangular grains have a natural geometric isomorphism. Taking a 510 mm × 515 mm panel as an example, even considering panel clamping, vacuum sealing, and edge plating effects, and retaining a 10 mm protective boundary on each of the four sides, its effective operating area still reaches:

Effective usable area = (510 – 20) × (515 – 20) = 490 × 495 = 242,550 mm²

The total area utilization rate reached:

Area utilization rate = 242,550 / 262,650 ≈ 92.35%

If the manufacturing process technology can compress the boundary width to 5 mm, the area utilization rate can easily reach over 95%.

For the same area, the "waste edge loss" of large-size square substrates is far lower than that of round wafers. For high-priced system-in-package (SiP) and chiplet modules that often integrate multiple chips, the additional 10% to 15% chip output is the key difference that affects the gross profit of chip mass production.

Physical challenges of large-size panels: Coefficient of thermal expansion (CTE) mismatch and warpage (Warpage)

Given the attractive size and cost-effectiveness of square panels, why didn't FOPLP sweep the entire advanced packaging market overnight?

There is only one answer:The larger the size, the more severe the backlash from the laws of physics. The most formidable engineering barrier is warpage.

Panel-level packaging is an artificial composite board made of multiple materials with very different properties stacked layer by layer. The main materials include:

• Silicon grainsIts coefficient of thermal expansion (CTE) is extremely low, approximately 2.6 to 3.0 ppm/°C.
• Copper RDL (Reconnect Layer Copper Metal)CTE is approximately 16 to 17 ppm/°C.
• Organic dielectric layer (Polyimide / PBO)CTE is approximately 30 to 60 ppm/°C.
• Epoxy molding compound (EMC)Below the glass transition temperature (Tg), it is approximately 7 to 15 ppm/°C; above Tg, it surges to over 30 to 50 ppm/°C.
• Temporary support carrier (Glass/Steel Carrier)For glass substrates, the concentration is approximately 3 to 8 ppm/°C; for metal stainless steel substrates, it is approximately 11 to 17 ppm/°C.

In the elastic bending theory of thin plate mechanics, the maximum deformation (warping displacement w) of a thin plate under thermal stress is proportional to the square of its characteristic length:

Warpage displacement w ∝ (Δα × ΔT × L²) / t

Where L is the characteristic side length of the substrate, t is the thickness, Δα is the difference in the coefficient of thermal expansion between the heterogeneous materials, and ΔT is the temperature difference between molding, baking and curing (150°C～175°C) and cooling to room temperature (25°C).

When the substrate size jumps from a 300 mm diameter circular wafer to a 600 mm square panel, the side length L doubles.This means that, under the same material thickness and temperature difference, the warping deformation driving force experienced by the panel-level substrate is more than 4 times that of the wafer-level substrate!

If warpage exceeds the allowable range (in practice, the global warpage of the panel is usually required to be less than 1 mm to 2 mm), it will cause a fatal process disaster:

1. The robotic arm failed to grasp the data.Vacuum suction cups cannot create a negative pressure seal on severely concave (smile) or convex (cry) panels, resulting in panels falling off or breaking during transport.
2. The depth of focus (DOF) exceeds the tolerance.High-resolution stepper exposure machines often have a depth of focus of only a few micrometers. If the panel still has local undulations at the level of hundreds of micrometers after being picked up by a vacuum chuck, the exposed pattern will be out of focus, resulting in blurred line widths, incomplete penetration of micro-vias, or even short circuits in the metal.

To delve deeper into how thermal stress accumulates in multilayer heterogeneous materials during reflow and cooling cycles, and how to measure thermal deformation in real time using optical methods such as shadow moiré, you can read more on this site about...Discussion on Thermal Deformation Issues of IC Packaging SubstratesA systematic analysis.

Molding material shrinkage and grain shift: alignment tolerance of redistribution layer (RDL)

Besides macroscopic panel warping, at the microscopic level...Grain shiftThis is the second major hurdle that affects FOPLP yield.

In the fan-out process, the die must first be temporarily fixed to the adhesive layer of the temporary carrier with high precision through a pick and place machine, and then sent into the mold for epoxy resin molding (EMC molding).

During the high-temperature curing process of compression molding, the epoxy resin polymer molecular chains cross-link with each other, resulting in significant...Chemical shrinkageThe typical shrinkage rate is between 0.2% and 0.8%; subsequently, when cooled from high temperature to room temperature, thermal expansion and cooling contraction occur. At the same time, when the molten resin flows at high speed in the mold cavity, the viscous drag force (Mold Sweep) generated on the wafer pushes the grains, causing micron-level translational displacement and θ rotation angle shift of the grains in the X and Y planes.

On a traditional 300 mm wafer, grain displacement can be controlled within ±2 µm to ±3 µm. However, on a huge panel of 500 mm to 600 mm, the non-uniform shrinkage torque can cause the grain displacement at the panel edge to soar to ±5 µm or even higher.

If the chip pad size to be connected in the first redistribution layer (RDL) is only 10 µm, and the diameter of the interlayer via is 5 µm, once the die displacement reaches 5 µm, the via will directly cut out the outer edge of the pad, causing an open circuit and scrap!

To suppress grain misalignment caused by molding compound flow and shrinkage, the packaging industry has completely shifted from traditional "transfer molding" to "vacuum liquid/granule compression molding," using vertical pressure to eliminate lateral flow erosion. For information on runner design, mold cavity pressure balance, and degassing valve construction for different packaging molds, please refer to the relevant sections on this website.Understanding Common IC Plastic Packaging MoldsA more in-depth explanation.

To address the already generated micro-grain displacement, equipment manufacturers have developed "Adaptive Patterning LithographyBefore applying the RDL, the exposure machine first uses a high-magnification optical system to scan the actual position of each die on the panel at high speed, dynamically calculates the offset matrix, and uses maskless digital lithography or local step adjustment to correct the coordinates of the exposure pattern at each point in real time, forcibly placing the RDL contacts precisely on the offset chip pads.

Glass substrates vs. metal substrates: The balance between process equipment modification and capital expenditure

In the FOPLP production line, the choice of material for the "temporary carrier" that supports the entire large-area module directly determines the warpage control capability and the subsequent process equipment architecture.

Currently, the industry is mainly weighing and comparing "glass carriers" and "metal carriers (mostly stainless steel)".

Glass substrates have become the mainstream carrier for high-end FOPLP (linewidth and line spacing ≤ 2 µm) due to their excellent flatness, adjustable CTE (which can closely approximate the equivalent expansion rate of silicon grains and EMC after curing), and support for penetrating ultraviolet laser exfoliation technology.

However, capital expenditure (CapEx) on substrates and equipment is a brutal financial problem. The equipment in 12-inch semiconductor wafer fabs (ASML, Applied Materials, Lam) has long formed a highly standardized equipment ecosystem; while the ultra-large size of panel-level packaging means that no single-wafer equipment can be directly reused.

The production line must be equipped with specialized stepper exposure machines, vertical continuous plating lines (VCP), dry film laminating machines, large-area CMP polishing machines, and automated optical inspection (AOI) equipment for large-size panels. The larger the panel size, the more precise the electrode shielding design and dynamic flow field control are required to maintain a copper plating thickness uniformity variation of less than 3% across a 600 mm span. This means that building a qualified advanced FOPLP mass production line from scratch requires an initial capital investment of tens of billions of New Taiwan Dollars.

This also explains why major Taiwanese panel manufacturers (such as Innolux) can demonstrate unique competitiveness when converting their old, fully depreciated 3.5-generation or even 4th-generation TFT-LCD factories into FOPLP production lines: because the cleanrooms and some panel-level photolithography infrastructure have been significantly depreciated, as long as they target the niche market where the packaging linewidth accuracy falls between 2 µm and 10 µm, they can enter the mid-to-high-end packaging field with amazing cost performance.

FOPLP is not about eliminating CoWoS, but about reshaping the distribution landscape of advanced packaging.

Returning to the core proposition of this article:Can panel-level fan-out package (FOPLP) solve CoWoS's production capacity shortage?

The evolution of technological development is not a zero-sum replacement of black and white, but rather a hierarchical division of labor:

1. CoWoS-S firmly holds the throne of "ultimate interconnect density".In the field of top-tier cloud training chips that require sub-micron metal traces to connect multiple HBM chips, the physical properties and heat dissipation stability of silicon interposers remain irreplaceable.
2. FOPLP conquers the high-performance, cost-effective market of "large-area multi-grain integration".In fields where the line spacing is greater than 2 µm and does not rely on extreme HBM interconnects, such as edge computing AI chips, autonomous driving computing modules, radio frequency front-end modules (RFEM), power management chips (PMIC), and large-size communication chips, FOPLP has unparalleled cost-per-unit competitiveness with a substrate utilization rate of more than 95% and a single batch capacity of many times.
3. Strategic "capacity reduction and diversion"When mid-range chips and communication modules that were originally squeezed into 12-inch wafer-level packaging (such as InFO or some CoWoS-R derivative architectures) are gradually transferred to the FOPLP square substrate production line, the precious 12-inch wafer foundry and CoWoS capacity can be released in large quantities to focus on supplying the highest-priced AI flagship chips.

For semiconductor engineers and hardware architecture decision-makers, evaluating packaging solutions should not involve blindly chasing the area gimmick of panel-level packaging. Only by thoroughly assessing the interconnect density requirements inside the chip, rigorously evaluating the warpage limits of heterogeneous materials under thermal cycling, and precisely calculating the critical point where equipment depreciation and yield loss cross, can the best balance between electrical performance and mass production efficiency be found in this packaging revolution from "circular" to "square".