Tag: Advanced Packaging

In-depth analysis of the positioning differences between panel-level fan-out packaging (FOPLP) and TSMC's CoWoS. Comparison of area utilization (>95% vs ~85%) and edge performance of square panels and round wafers.

Nvidia's investment in MediaTek's overseas convertible bonds is more than just a financial investment. This article deciphers the chip engineering architecture: analyzing cloud-based custom ASICs and NVLink Fusion interconnects.

Why is advanced packaging shifting from ABF organic substrates to glass substrates? This article compares the coefficients of thermal expansion (CTE), flatness, and TGV glass via yield challenges of silicon interlayers, ABF, and glass substrates.

CPO (Commonly Packaged Optics) moves the optical engine next to the switch chip, shortening the high-speed signal path. This article analyzes its operating principle, its differences from pluggable optical modules, its applications in AI data centers, and its heat dissipation and maintenance.

Taiwan's role in the AI supply chain extends beyond chip manufacturing; it also encompasses advanced packaging, substrate materials, server rack cooling, and power upgrades. This article uses a relatable perspective to analyze bottlenecks and trends, helping you understand "capacity expansion," "liquid cooling," and more.