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With the maturation of semiconductor technology, packaging has become increasingly crucial in the modern era, playing a pivotal role in the semiconductor industry. Apple's M-series chips, for instance, heavily rely on TSMC's breakthrough packaging technology. This reliance has enabled subsequent products to achieve a lightweight design while maintaining exceptional performance. Especially in future wearable devices like VR goggles, there is an increased demand for lightweight components. This underscores the growing importance of packaging technology. The ability to shrink the volume of transistors while maintaining high efficiency, aside from relying on EUV lithography, emphasizes the significant role of packaging technology.
What is packaging? What does the packaging and testing factory do?
Simply put, packaging is the process of placing one or more semiconductor components or integrated circuits onto a substrate, encasing them in an outer shell to protect the chips from external environmental influences, and providing interfaces for connection to external circuits.
Packaging is the final step in the semiconductor manufacturing process and a crucial aspect in commercializing semiconductor products.
The packaging process generally involves four main steps: testing, cutting, die attachment, wire bonding, and encapsulation.
測試
First, the packaging and testing facility obtains wafers (referred to as "wafer," with a biscuit analogy for its shape) from manufacturers such as TSMC and UMC. Each wafer consists of numerous bare dies (referred to as "die," likened to dice due to their square shape).
Next, the wafers are sent for testing, where probe needles are used to perform electrical measurements on the bare dies. The obtained signals are then sent to the equipment to assess the performance. Dies that do not meet the specifications are marked as defective.
切割
After testing, the wafers undergo a cutting process to separate each individual die.
黏晶
During the probing process, the unmarked dies are picked and attached to a carrier board.
打線
Metallic points are welded to establish electrical connections between the bare dies and the carrier board, enabling the transmission of signals in the integrated circuit.
封膠
The entire assembly of bare dies and the carrier board is placed into a mold, and epoxy resin is poured in. After cooling, a protective layer and outer casing are formed.
The completed process results in what we commonly refer to as a chip (IC), and the assembly is done by the packaging and testing facility.
The emergence of advanced packaging
隨著時代的演進，晶片已經不單單只是單一晶片的功能了，而是必須同時包含多個晶片功能整合在一起。而這樣的技術我們稱為”Chiplet”，其中Apple的M2晶片就是整合了CPU、GPU和記憶體在一起。 我們常見的Chiplet技術包含了兩種工藝，分別是SoC 與 SiP。 系統單晶片SoC（System on Chip）是將數個不同晶片，全部使用「同製程工藝」，並整合於單一晶片上；而 系統級封裝SiP（System in Package），是將數個「不同製程工藝」的晶片，透過異質整合技術對其進行連接，並整合於同一個封裝殼內。 而以上傳統的模式都需要占用較大的面積，且傳輸速度也不盡理想，因此先進封裝技術才正式登場。 先進封裝技術採用了三維封裝技術，而目前最夯的CoWoS就是3D封裝技術。 CoWoS可以分成「CoW（Chip-on-Wafer）」和「WoS（Wafer-on-Substrate）」，CoW是把不同晶片堆疊；WoS則是將堆疊晶片封裝到基板上。所以CoWoS 就是把晶片堆疊起來，再封裝於基板上，最終形成三維的型態，可以減少晶片的空間，也縮短了金屬線傳輸的路徑，大幅提升訊號的傳遞速度，也有效能降低成本。
Currently, advanced packaging technologies face challenges with process nodes below 7nm. Traditional packaging facilities struggle to keep up with the precision of wafer manufacturing. This is why TSMC offers end-to-end services, as they are currently the only company capable of achieving such precision. Looking ahead, there are still many challenges for advanced packaging to overcome, with heat dissipation being a primary concern. The trend towards smaller and denser integrated circuits leads to increased heat generation during the operation of various integrated circuits, resulting in a significant reduction in performance.
As a primary driver of Moore's Law, advanced packaging has many challenges ahead. In addition to TSMC needing to stabilize CoWoS yield rates, the capability of other packaging and testing facilities to keep pace is a crucial factor influencing global semiconductor development.
